Towards Autonomous Accelerator Design: FPGA Accelerator Generation with SECDA
English summary
SECDA-DSE is a framework that integrates Large Language Models into the SECDA ecosystem for design space exploration of FPGA-based accelerators. It combines a structured DSE Explorer with an LLM Stack using retrieval-augmented generation and chain-of-thought prompting, along with an iterative feedback loop for refinement. The paper extends the evaluation by generating three accelerator designs—element-wise vector multiplication, 2D convolution, and matrix transpose—and performing end-to-end execution on FPGA hardware. Results show that SECDA-DSE produces SECDA-compliant designs that are successfully synthesized and executed on FPGA, capturing kernel-specific trade-offs between compute parallelism and data movement. This demonstrates the potential of LLM-guided exploration to adapt architectural configurations across diverse workloads while reducing exploration time and the need for extensive human expertise.
Chinese summary
SECDA-DSE框架将大语言模型集成到SECDA生态中，用于FPGA加速器的设计空间探索。它结合了结构化DSE探索器和采用检索增强生成与思维链提示的LLM栈，并通过迭代反馈回路进行优化。论文扩展了评估范围，生成了逐元素向量乘法、二维卷积和矩阵转置三种加速器设计，并在FPGA硬件上实现了端到端执行。结果表明，SECDA-DSE能生成符合SECDA规范的设计，成功在FPGA上合成并执行，捕捉了计算并行性与数据传输之间的特定内核权衡。这展示了LLM引导探索在不同工作负载下调整架构配置的潜力，同时减少了探索时间和对大量人类专业知识的需求。
Key points
SECDA-DSE integrates LLMs into the SECDA framework for automated FPGA accelerator design space exploration, using RAG and chain-of-thought with iterative feedback.
SECDA-DSE将大语言模型集成到SECDA框架中，利用检索增强生成和思维链及迭代反馈实现FPGA加速器设计空间自动化探索。
Three accelerator designs (element-wise vector multiplication, 2D convolution, matrix transpose) were generated, synthesized, and successfully executed on FPGA hardware.
生成了逐元素向量乘法、二维卷积和矩阵转置三种加速器设计，在FPGA硬件上成功合成并执行。
The generated designs capture trade-offs between compute parallelism and data movement, showing LLM-guided exploration can adapt to diverse workloads.
生成的设计捕捉了计算并行性与数据移动之间的权衡，表明LLM引导的探索能适应多种工作负载。